4 / April 19, 2014
(4.2/5) (6)
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Description

Arrange the colored objects. Use as fewmovesas possible.

App Information Color Line Puzzle

  • App Name
    Color Line Puzzle
  • Package Name
    com.hexastyle.colorlinepuzzle
  • Updated
    April 19, 2014
  • File Size
    1.3M
  • Requires Android
    Android 2.2 and up
  • Version
    4
  • Developer
    Hexastyle
  • Installs
    500 - 1,000
  • Price
    Free
  • Category
    Puzzle
  • Developer
  • Google Play Link

Hexastyle Show More...

Logic Breadboard Simulator 2.9 APK
Hexastyle
Logic Breadboard Simulator is a logic circuitsimulator with breadboard and schematic editors, HDL input, virtualdigital oscilloscope.The breadboard has the following features.Power connectors, two independent clock generators, scope with 32channels.Single touch hole and device selection. Wire to resistor,LED,LED+resistor transformation. Device library. 7 step undo/redo.Custom circuits.7 segment display.ICs:7400, 7401, 7402, 7403, 7404, 7405, 7406, 7407,7408, 7409, 7410,7411, 7412, 7413, 7414, 7415, 7416, 7417, 7419, 7420, 7421, 7422,7427, 7428, 7430, 7440, 7449Currently available schematic components:Transistors: NMOS, PMOSLogic gates: buffer, inverter, and, nand, or, nor, exor, exnor,tri-state buffer and inverterFlip flops: D latch, edge triggered D, JK flip flops,monostableMultiplexers: 2 to 1, 4 to 1, 8 to 1.Demultiplexers: 1 to 2, 1 to 4, 1 to 8Indicators: LED, oscilloscope probeDisplays: decimal, hexadecimalSwitches: toggle button, push buttonConstants: high and low.The scheme editor comes from & logics app with someimprovements.Four times bigger canvas, faster router. Sub circuits on breadboardmay have port labels.Simply put an annotation to the circuit. The syntax is simple.Start with . and separate labels with dots. If the port is negatedthan start label with ~. The number of port labels must be equal tothe number of ports.E.g..B.C.~LT.~BI/RBO.~RBI.D.A.GND.e.d.c.b.a.g.f.VccThe place of the custom circuits is the "ics" directory.Scheme editor features: custom subcircuit (black box), contextsensitive menu, autorouter, 7 steps undo/redo, labels for farconnections, automatic enlarge on selection, cloning, rotating,locked and unlocked move, vertical and horizontal alignment, moveto center.The digital circuit simulator works with three logic levels andthree impedance values. They are low, undefined and high.Wires optionally can display logic levels.Switch level modelling, gate level modelling and complex devicelevel modelling can be mixed in a circuit.The simulator detects run time errors and puts error messages onthe schematic.Detected errors are:Temporary short circuit conditions. When connected outputs havedifferent or undefined levels and have low or undefinedimpedance.Spike detection. When an input receives an impulse shorter than theconfigured value.Flip flop setup, hold, recovery, resume time violations. Flip flopsmay enter a metastable state in these cases.The virtual digital oscilloscope has the following currentfeatures: start, stop time, buffer length setting, time shift andzoom, up/down scroll, display of logical low, high, and undefinedstates.The app contains HDL extension. It is possible to describe acircuit in a box using a very small subset of Verilog. The gates.sdemo loads the following module from simple.v file:module smpl_circuit (A,B,AND,NAND,OR,NOR,XOR,XNOR,BUF,NOT);input A,B;output AND,NAND,OR,NOR,XOR,XNOR,BUF,NOT;and #10 g0(AND,A,B);nand #10 g1(NAND,A,B);or #10 g2(OR,A,B);nor #10 g3(NOR,A,B);xor #10 g4(XOR,A,B);xnor #10 g5(XNOR,A,B);buf #10 g6(BUF,A);not #10 (NOT,A);endmoduleand the test1.v file:module circuit(A,B,C,y);input A,B;output y;wire e;and #30 g1(e,A,B);or #30 g2(y,e,C);endmoduleThere is no runtime error detection inside the boxes.Only the first compile time error is displayed.The program comes with built in demo circuits. They help you to getstarted quickly.See http://www.hexastyle.com/home/andlogics/first-3-steps fordetails.You can easily simulate, analyse and modify operation and timing ofthe examples.Built in examples:74160, 74163 synchronous counter74180 parity generator checker74181 4 bit ALU74147, 74148 priority encodertransistor level modelling of CMOS gatesMore examples can be downloaded from here:http://www.hexastyle.com/home/andlogics/download-examples
& logics 5.7 APK
Hexastyle
& logics is a logic circuit simulator withan integrated scheme editor and a waveform browser.Currently available schematic components:Transistors: NMOS, PMOSLogic gates: buffer, inverter, and, nand, or, nor, exor, exnor,tri-state buffer and inverterFlip flops: D latch, edge triggered D, JK flip flops,monostableMultiplexers: 2 to 1, 4 to 1, 8 to 1.Demultiplexers: 1 to 2, 1 to 4, 1 to 8Indicators: LED, oscilloscope probeDisplays: decimal, hexadecimalSwitches: toggle button, push buttonConstants: high and low.Scheme editor features: custom subcircuit (black box), contextsensitive menu, autorouter, 7 steps undo/redo, labels for farconnections, automatic enlarge on selection, cloning, rotating,locked and unlocked move, vertical and horizontal alignment, moveto center.The digital circuit simulator works with three logic levels andthree impedance values. They are low, undefined and high.Wires optionally can display logic levels.Switch level modelling, gate level modelling and complex devicelevel modelling can be mixed in a circuit.The simulator detects run time errors and puts error messages onthe schematic.Detected errors are:Temporary short circuit conditions. When connected outputs havedifferent or undefined levels and have low or undefinedimpedance.Spike detection. When an input receives an impulse shorter than theconfigured value.Flip flop setup, hold, recovery, resume time violations. Flip flopsmay enter a metastable state in these cases.The waveform browser is a virtual digital oscilloscope. The currentfeatures are: start, stop time, buffer length setting, time shiftand zoom, display of logical low, high, and undefined states.The 3.x releases contain HDL extension. It is possible to describea circuit in a box using a very small subset of Verilog. Thegates.s demo loads the following module from simple.v file:module smpl_circuit (A,B,AND,NAND,OR,NOR,XOR,XNOR,BUF,NOT);input A,B;output AND,NAND,OR,NOR,XOR,XNOR,BUF,NOT;and #10 g0(AND,A,B);nand #10 g1(NAND,A,B);or #10 g2(OR,A,B);nor #10 g3(NOR,A,B);xor #10 g4(XOR,A,B);xnor #10 g5(XNOR,A,B);buf #10 g6(BUF,A);not #10 (NOT,A);endmoduleand the test1.v file:module circuit(A,B,C,y);input A,B;output y;wire e;and #30 g1(e,A,B);or #30 g2(y,e,C);endmoduleThere is no runtime error detection inside the boxes.Only the first compile time error is displayed.The program comes with built in demo circuits. They help you to getstarted quickly.See http://www.hexastyle.com/home/andlogics/first-3-steps fordetails.You can easily simulate, analyse and modify operation and timing ofthe examples.Built in examples:74160, 74163 synchronous counter74180 parity generator checker74181 4 bit ALU74147, 74148 priority encodertransistor level modelling of CMOS gatesMore examples e.g. binary adder, Johnson counter can be downloadedfrom here:http://www.hexastyle.com/home/andlogics/download-examples
Logic Breadboard 2.9 APK
Hexastyle
Logic Breadboard Simulator is a logic circuitsimulator with breadboard and schematic editors, HDL input, virtualdigital oscilloscope.The breadboard has the following features.Power connectors, two independent clock generators, scope with 32channels.Single touch hole and device selection. Wire to resistor,LED,LED+resistor transformation. Device library. 7 step undo/redo.Custom circuits.7 segment display.ICs:7400, 7401, 7402, 7403, 7404, 7405, 7406, 7407,7408, 7409, 7410,7411, 7412, 7413, 7414, 7415, 7416, 7417, 7419, 7420, 7421, 7422,7427, 7428, 7430, 7440, 7449Currently available schematic components:Transistors: NMOS, PMOSLogic gates: buffer, inverter, and, nand, or, nor, exor, exnor,tri-state buffer and inverterFlip flops: D latch, edge triggered D, JK flip flops,monostableMultiplexers: 2 to 1, 4 to 1, 8 to 1.Demultiplexers: 1 to 2, 1 to 4, 1 to 8Indicators: LED, oscilloscope probeDisplays: decimal, hexadecimalSwitches: toggle button, push buttonConstants: high and low.The scheme editor comes from & logics app with someimprovements.Four times bigger canvas, faster router. Sub circuits on breadboardmay have port labels.Simply put an annotation to the circuit. The syntax is simple.Start with . and separate labels with dots. If the port is negatedthan start label with ~. The number of port labels must be equal tothe number of ports.E.g..B.C.~LT.~BI/RBO.~RBI.D.A.GND.e.d.c.b.a.g.f.VccThe place of the custom circuits is the "ics" directory.Scheme editor features: custom subcircuit (black box), contextsensitive menu, autorouter, 7 steps undo/redo, labels for farconnections, automatic enlarge on selection, cloning, rotating,locked and unlocked move, vertical and horizontal alignment, moveto center.The digital circuit simulator works with three logic levels andthree impedance values. They are low, undefined and high.Wires optionally can display logic levels.Switch level modelling, gate level modelling and complex devicelevel modelling can be mixed in a circuit.The simulator detects run time errors and puts error messages onthe schematic.Detected errors are:Temporary short circuit conditions. When connected outputs havedifferent or undefined levels and have low or undefinedimpedance.Spike detection. When an input receives an impulse shorter than theconfigured value.Flip flop setup, hold, recovery, resume time violations. Flip flopsmay enter a metastable state in these cases.The virtual digital oscilloscope has the following currentfeatures: start, stop time, buffer length setting, time shift andzoom, up/down scroll, display of logical low, high, and undefinedstates.The app contains HDL extension. It is possible to describe acircuit in a box using a very small subset of Verilog. The gates.sdemo loads the following module from simple.v file:module smpl_circuit (A,B,AND,NAND,OR,NOR,XOR,XNOR,BUF,NOT);input A,B;output AND,NAND,OR,NOR,XOR,XNOR,BUF,NOT;and #10 g0(AND,A,B);nand #10 g1(NAND,A,B);or #10 g2(OR,A,B);nor #10 g3(NOR,A,B);xor #10 g4(XOR,A,B);xnor #10 g5(XNOR,A,B);buf #10 g6(BUF,A);not #10 (NOT,A);endmoduleand the test1.v file:module circuit(A,B,C,y);input A,B;output y;wire e;and #30 g1(e,A,B);or #30 g2(y,e,C);endmoduleThere is no runtime error detection inside the boxes.Only the first compile time error is displayed.The program comes with built in demo circuits. They help you to getstarted quickly.See http://www.hexastyle.com/home/andlogics/first-3-steps fordetails.You can easily simulate, analyse and modify operation and timing ofthe examples.Built in examples:74160, 74163 synchronous counter74180 parity generator checker74181 4 bit ALU74147, 74148 priority encodertransistor level modelling of CMOS gatesMore examples e.g. binary adder, Johnson counter can be downloadedfrom here:http://www.hexastyle.com/home/andlogics/download-examples
Color Line Puzzle 4 APK
Hexastyle
Arrange the colored objects. Use as fewmovesas possible.
HEXDCM Test 1.0 APK
Hexastyle
Diagnose DICOM servers easily. Retrievestatusand capabilities by a few clicks.Hexdcm Test helps to check the connection to a DICOM ServiceClassProvider.The application maintains a host database containing AE Titles,IPaddresses, port numbers, PDU sizes, transfer syntaxes. Itispossible to send C-ECHO request to the selected host. In thiscasethe transfer syntax parameter comes from the host database.Anothertest possibility is sending association request withdatabaseindependent transfer syntax.
Hexdcm Demo 1.0 APK
Hexastyle
Hexdcm Demo fetches patient data from aremotedatabase, merges data with a selected photo and stores themon aserver. The application contains a Modality Worklist SCU andaStorage SCU. They are built on Hexdcm DICOM SCU core.Theapplication has a host database. It can store AE Title, IPaddress,port number, PDU size limit, server type, allowed tags andtransfersyntax parameters. The application can send C-FIND andC-STORErequests. The worklist database can be accessed with patientnamekey. This one key restriction is applied to this demo only. Itispossible to store jpeg images together default, queried ormanuallyset data. This demo does no data check. Images will beconverted toRGB format before the transfer. Although this is ademoapplication, it is useful for testing an SCP.
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